ARM Assembly Language Fundamentals and Techniques 2nd Edition by William Hohl ISBN 1482229854 9781482229851

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ISBN 10: 1482229854

ISBN 13: 9781482229851

Author: William Hohl

Table of contents: 

1 An Overview of Computing Systems
1.1 INTRODUCTION
FIGURE 1.1 Handheld wireless communicator.
FIGURE 1.2 The TMS320DM355 System-on-Chip from Texas Instruments.
1.2 HISTORY OF RISC
1.2.1 ARM Begins
FIGURE 1.3 ARM2 microprocessor.
1.2.2 The Creation of ARM Ltd.
FIGURE 1.4 The ARM7TDMI.
FIGURE 1.5 Architecture versions.
1.2.3 ARM Today
1.2.4 The Cortex Family
1.2.4.1 The Cortex-A and Cortex-R Families
1.2.4.2 The Cortex-M Family
FIGURE 1.6 Tiva LaunchPad from Texas Instruments.
1.3 THE COMPUTING DEVICE
FIGURE 1.7 Hollerith cards.
FIGURE 1.8 The stored-program computer model.
FIGURE 1.9 Hierarchy of computing.
1.4 NUMBER SYSTEMS
EXAMPLE 1.1
FIGURE 1.10 Base ten representation of 438.
EXAMPLE 1.2
EXAMPLE 1.3
TABLE 1.1 Binary and Hexadecimal Equivalents
EXAMPLE 1.4
1.5 REPRESENTATIONS OF NUMBERS AND CHARACTERS
1.5.1 Integer Representations
EXAMPLE 1.5
EXAMPLE 1.6
EXAMPLE 1.7
EXAMPLE 1.8
TABLE 1.2 Two’s Complement Integer Ranges
EXAMPLE 1.9
1.5.2 Floating-Point Representations
EXAMPLE 1.10
FIGURE 1.11 Formation of 1.5 in single-precision.
TABLE 1.3 IEEE 754 Single- and Double-Precision Formats
1.5.3 Character Representations
1.6 TRANSLATING BITS TO COMMANDS
EXAMPLE 1.11
FIGURE 1.12 The MOV instruction.
1.7 THE TOOLS
FIGURE 1.13 Tools flow.
1.7.1 Open Source Tools
1.7.2 Keil (ARM)
FIGURE 1.14 Keil simulation tools.
1.7.3 Code Composer Studio
FIGURE 1.15 Code Composer Studio development tools.
1.7.4 Useful Documentation
1.8 EXERCISES
2 The Programmer’s Model
2.1 INTRODUCTION
2.2 DATA TYPES
2.3 ARM7TDMI
2.3.1 Processor Modes
FIGURE 2.1 Processor modes.
2.3.2 Registers
FIGURE 2.2 Register organization.
FIGURE 2.3 ARM7TDMI pipeline diagram.
FIGURE 2.4 Format of the program status registers.
TABLE 2.1 The Mode Bits
2.3.3 The Vector Table
TABLE 2.2 ARM7TDMI Exception Vectors
2.4 CORTEX-M4
2.4.1 Processor Modes
2.4.2 Registers
FIGURE 2.5 Cortex-M4 modes.
FIGURE 2.6 Cortex-M4 with floating-point register organization.
FIGURE 2.7 Program status registers on the Cortex-M4.
2.4.3 The Vector Table
TABLE 2.3 Cortex-M4 Exception Vectors
2.5 EXERCISES
3 Introduction to Instruction Sets: v4T and v7-M
3.1 INTRODUCTION
3.2 ARM, THUMB, AND THUMB-2 INSTRUCTIONS
3.3 PROGRAM 1: SHIFTING DATA
3.3.1 Running the Code
FIGURE 3.1 Disassembly window.
FIGURE 3.2 Bit pattern for a branch instruction.
3.3.2 Examining Register and Memory Contents
FIGURE 3.3 Register and memory windows in the Keil tools.
FIGURE 3.4 Register and memory windows in CCS.
3.4 PROGRAM 2: FACTORIAL CALCULATION
3.5 PROGRAM 3: SWAPPING REGISTER CONTENTS
3.6 PROGRAM 4: PLAYING WITH FLOATING-POINT NUMBERS
FIGURE 3.5 Register window in the Keil tools.
3.7 PROGRAM 5: MOVING VALUES BETWEEN INTEGER AND FLOATING-POINT REGISTERS
3.8 PROGRAMMING GUIDELINES
3.9 EXERCISES
4 Assembler Rules and Directives
4.1 INTRODUCTION
4.2 STRUCTURE OF ASSEMBLY LANGUAGE MODULES
TABLE 4.1 ARM Version 4T Instruction Set
4.3 PREDEFINED REGISTER NAMES
4.4 FREQUENTLY USED DIRECTIVES
4.4.1 Defining a Block of Data or Code
TABLE 4.2 Frequently Used Directives
4.4.1.1 Keil Tools
EXAMPLE 4.1
TABLE 4.3 Valid Section Attributes (Keil Tools)
4.4.1.2 Code Composer Studio Tools
TABLE 4.4 TI Assembler Section Directives
4.4.2 Register Name Definition
4.4.2.1 Keil Tools
EXAMPLE 4.2
4.4.2.2 Code Composer Studio
4.4.3 Equating a Symbol to a Numeric Constant
4.4.3.1 Keil Tools
EXAMPLE 4.3
4.4.3.2 Code Composer Studio
EXAMPLE 4.4
4.4.4 Declaring an Entry Point
EXAMPLE 4.5
4.4.5 Allocating Memory and Specifying Contents
4.4.5.1 Keil Tools
EXAMPLE 4.6
EXAMPLE 4.7
4.4.5.2 Code Composer Studio
EXAMPLE 4.8
4.4.6 Aligning Data or Code to Appropriate Boundaries
4.4.6.1 Keil Tools
EXAMPLE 4.9
4.4.6.2 Code Composer Studio
4.4.7 Reserving a Block of Memory
4.4.7.1 Keil Tools
EXAMPLE 4.10
4.4.7.2 Code Composer Studio
EXAMPLE 4.11
4.4.8 Assigning Literal Pool Origins
EXAMPLE 4.12
4.4.9 Ending a Source File
4.5 MACROS
EXAMPLE 4.13
4.6 MISCELLANEOUS ASSEMBLER FEATURES
4.6.1 Assembler Operators
EXAMPLE 4.14
4.6.2 Math Functions in CCS
EXAMPLE 4.15
4.7 EXERCISES
5 Loads, Stores, and Addressing
5.1 INTRODUCTION
5.2 MEMORY
TABLE 5.1 Memory Map of the Tiva TM4C123GH6ZRB
5.3 LOADS AND STORES: THE INSTRUCTIONS
TABLE 5.2 Most Often Used Load/Store Instructions
EXAMPLE 5.1
EXAMPLE 5.2
TABLE 5.3 Addressing Options for Loads and Stores on the ARM7TDMI
TABLE 5.4 Addressing Options for Loads and Stores on the Cortex-M4
EXAMPLE 5.3
5.4 OPERAND ADDRESSING
5.4.1 Pre-Indexed Addressing
FIGURE 5.1 Pre-indexed store operation.
5.4.2 Post-Indexed Addressing
FIGURE 5.2 Post-indexed store operation.
EXAMPLE 5.4
5.5 ENDIANNESS
FIGURE 5.3 Little-endian memory configuration.
FIGURE 5.4 Big-endian memory configuration.
FIGURE 5.5 Little-endian addressing of an instruction.
5.5.1 Changing Endianness
5.5.2 Defining Memory Areas
5.6 BIT-BANDED MEMORY
FIGURE 5.6 Mapping bit-banded regions.
5.7 MEMORY CONSIDERATIONS
FIGURE 5.7 Keil memory map tile.
FIGURE 5.8 Code Composer Studio linker command file.
5.8 EXERCISES
6 Constants and Literal Pools
6.1 INTRODUCTION
6.2 THE ARM ROTATION SCHEME
FIGURE 6.1 MOV instruction.
FIGURE 6.2 MOV instruction with an immediate operand.
FIGURE 6.3 Byte rotated by an even number of bits.
FIGURE 6.4 ARM7 internal datapaths.
TABLE 6.1 Examples of Creating Constants with Rotation
EXAMPLE 6.1
EXAMPLE 6.2
FIGURE 6.5 MOV operation using a 32-bit Thumb instruction.
6.3 LOADING CONSTANTS INTO REGISTERS
FIGURE 6.6 Disassembly of ARM7TDMI program.
FIGURE 6.7 LDR instruction in Thumb and Thumb-2.
6.4 LOADING CONSTANTS WITH MOVW, MOVT
EXAMPLE 6.3
6.5 LOADING ADDRESSES INTO REGISTERS
EXAMPLE 6.4
EXAMPLE 6.5
6.6 EXERCISES
7 Integer Logic and Arithmetic
7.1 INTRODUCTION
7.2 FLAGS AND THEIR USE
FIGURE 7.1 Status registers.
7.2.1 The N Flag
EXAMPLE 7.1
EXAMPLE 7.2
FIGURE 7.2 Status flags in the CPSR.
7.2.2 The V Flag
EXAMPLE 7.3
FIGURE 7.3 Status flags indicating an overflow.
7.2.3 The Z Flag
EXAMPLE 7.4
7.2.4 The C Flag
7.3 COMPARISON INSTRUCTIONS
7.4 DATA PROCESSING OPERATIONS
7.4.1 Boolean Operations
TABLE 7.1 Boolean Operations
7.4.2 Shifts and Rotates
FIGURE 7.4 The ARM7TDMI barrel shifter.
FIGURE 7.5 Shifts and rotates.
EXAMPLE 7.5
EXAMPLE 7.6
EXAMPLE 7.7
Original 8-bit value
Modified 8-bit value
7.4.3 Addition/Subtraction
EXAMPLE 7.8
EXAMPLE 7.9
FIGURE 7.6 64-bit addition.
EXAMPLE 7.10
7.4.4 Saturated Math Operations
FIGURE 7.7 Signal represented by 16-bit signed integers.
FIGURE 7.8 Digital waveform exceeding bounds.
FIGURE 7.9 Digital waveform with saturation.
EXAMPLE 7.11
FIGURE 7.10 16-bit unsigned signal.
EXAMPLE 7.12
7.4.5 Multiplication
TABLE 7.2 ARM7TDMI Multiply and Multiply-Accumulate Instructions
EXAMPLE 7.13
7.4.6 Multiplication by a Constant
FIGURE 7.11 ARM10200 die photo with multiplier array highlighted.
7.4.7 Division
EXAMPLE 7.14
7.5 DSP EXTENSIONS
EXAMPLE 7.15
FIGURE 7.12 Operations involved in SMMLA and SMMLAR.
EXAMPLE 7.16
7.6 BIT MANIPULATION INSTRUCTIONS
FIGURE 7.13 Unsigned bit field extract instruction.
7.7 FRACTIONAL NOTATION
FIGURE 7.14 Binary interpretations of fractional values.
EXAMPLE 17.7
EXAMPLE 7.18
EXAMPLE 7.19
EXAMPLE 7.20
7.8 EXERCISES
8 Branches and Loops
8.1 INTRODUCTION
8.2 BRANCHING
FIGURE 8.1 ARM7TDMI pipeline diagram.
8.2.1 Branching (ARM7TDMI)
FIGURE 8.2 The B and BL instruction.
TABLE 8.1 Condition Codes and Their Meaning
EXAMPLE 8.1
FIGURE 8.3 Flowchart for normalization algorithm.
8.2.2 Version 7-M Branches
8.3 LOOPING
8.3.1 While Loops
8.3.2 For Loops
EXAMPLE 8.2
EXAMPLE 8.3
FIGURE 8.4 Flowchart for summing six integers.
8.3.3 Do-While Loops
8.4 CONDITIONAL EXECUTION
8.4.1 v4T Conditional Execution
FIGURE 8.5 Condition code field.
FIGURE 8.6 32-bit wide Thumb instruction.
EXAMPLE 8.4
EXAMPLE 8.5
8.4.2 v7-M Conditional Execution: The IT Block
EXAMPLE 8.6
8.5 STRAIGHT-LINE CODING
8.6 EXERCISES
9 Introduction to Floating-Point: Basics, Data Types, and Data Transfer
9.1 INTRODUCTION
9.2 A BRIEF HISTORY OF FLOATING-POINT IN COMPUTING
FIGURE 9.1 Konrad Zuse with a reconstruction of the Z3 computer.
FIGURE 9.2 IBM 7094 System.
FIGURE 9.3 Seymore Cray and a Cray-1 Computer, circa 1974.
FIGURE 9.4 Dr. William Kahan.
9.3 THE CONTRIBUTION OF FLOATING-POINT TO THE EMBEDDED PROCESSOR
9.4 FLOATING-POINT DATA TYPES
FIGURE 9.5 IEEE 754-2008 data formats.
EXAMPLE 9.1
TABLE 9.1 Floating-Point Formats and Their Characteristics
FIGURE 9.6 Result of Example 9.1.
EXAMPLE 9.2
FIGURE 9.7 Result of Example 9.2.
9.5 THE SPACE OF FLOATING-POINT REPRESENTABLE VALUES
FIGURE 9.8 Floating-point number line for positive values, 2 exponent bits and 2 fractional bits (see Ercegovac and Lang 2004).
TABLE 9.2 Examples of the Range of Numeric Separation in Single-Precision Values
9.6 FLOATING-POINT REPRESENTABLE VALUES
9.6.1 Normal Values
FIGURE 9.9 Relative normal range for signed 32-bit integer, half-precision floating-point, and single-precision floating-point data types.
TABLE 9.3 Several Normal Half-Precision and Single-Precision Floating-Point Values
9.6.2 Subnormal Values
TABLE 9.4 Subnormal Range for Half-Precision and Single-Precision
EXAMPLE 9.3
TABLE 9.5 Examples of Subnormal Values for Half-Precision and Single-Precision
FIGURE 9.10 Single-precision representation of −4.592 × 10−41.
9.6.3 Zeros
EXAMPLE 9.4
TABLE 9.6 Operations with Zero Result in Each Rounding Mode
TABLE 9.7 Format of Signed Zero in Half-Precision and Single-Precision
9.6.4 Infinities
TABLE 9.8 Format of Signed Infinity in Half-Precision and Single-Precision
9.6.5 Not-a-Numbers (NaNs)
TABLE 9.9 Format of NaN Encodings in Half-Precision and Single-Precision
TABLE 9.10 Examples of Quiet and Signaling NaNs in Half-Precision and Single-Precision Formats
9.7 THE FLOATING-POINT REGISTER FILE OF THE CORTEX-M4
FIGURE 9.11 Cortex-M4 floating-point register file.
9.8 FPU CONTROL REGISTERS
9.8.1 The Floating-Point Status and Control Register, FPSCR
FIGURE 9.12 Cortex-M4 Floating-Point Status and Control Register.
9.8.1.1 The Control and Mode Bits
TABLE 9.11 Format of the Default Nan for Half-Precision and Single-Precision Data Types
TABLE 9.12 Rounding Mode Bits
9.8.1.2 The Exception Bits
TABLE 9.13 FPSCR Exception Bits
9.8.2 The Coprocessor Access Control Register, CPACR
FIGURE 9.13 Cortex-M4 Coprocessor Access Control Register.
9.9 LOADING DATA INTO FLOATING-POINT REGISTERS
9.9.1 Floating-Point Loads and Stores: The Instructions
9.9.2 The VMOV instruction
TABLE 9.14 Data Type Identifiers
FIGURE 9.14 VMOV immediate instruction.
FIGURE 9.15 Formation of constants using the VMOV immediate instruction.
FIGURE 9.16 Formation of 1.0 using VMOV immediate instruction.
9.10 CONVERSIONS BETWEEN HALF-PRECISION AND SINGLE-PRECISION
TABLE 9.15 Useful Floating-Point Constants
9.11 CONVERSIONS TO NON-FLOATING-POINT FORMATS
9.11.1 Conversions between Integer and Floating-Point
9.11.2 Conversions between Fixed-Point and Floating-Point
EXAMPLE 9.5
TABLE 9.16 Output of Example 9.5
TABLE 9.17 Ranges of Available 16-Bit Fixed-Point Format Data
9.12 EXERCISES
10 Introduction to Floating-Point: Rounding and Exceptions
10.1 INTRODUCTION
10.2 ROUNDING
FIGURE 10.1 Possible results between two representable values.
10.2.1 Introduction to Rounding Modes in the IEEE 754-2008 Specification
FIGURE 10.2 Internal representation of 224 + 1.25.
EXAMPLE 10.1
10.2.2 The roundTiesToEven (RNE) Rounding Mode
TABLE 10.1 Significand with Guard and Sticky Bits
TABLE 10.2 roundTiesToEven Rounding Summary
EXAMPLE 10.2
EXAMPLE 10.3
EXAMPLE 10.4
10.2.3 The Directed Rounding Modes
10.2.3.1 The roundTowardPositive (RP) Rounding Mode
10.2.3.2 The roundTowardNegative (RM) Rounding Mode
10.2.3.3 The roundTowardZero (RZ) Rounding Mode
10.2.4 Rounding Mode Summary
EXAMPLE 10.5
FIGURE 10.3 Rounding mode summary.
TABLE 10.3 Rounding Mode Summary
TABLE 10.4 Operands for Example 10.5
TABLE 10.5 Example 10.5 Intermediate Values
10.3 EXCEPTIONS
10.3.1 Introduction to Floating-Point Exceptions
10.3.2 Exception Handling
10.3.3 Division by Zero
EXAMPLE 10.6
FIGURE 10.4 Output of Example 10.6.
FIGURE 10.5 FPSCR Contents after Example 10.6.
10.3.4 Invalid Operation
TABLE 10.6 Operations and Operands Signaling the Invalid Operation Exception
10.3.5 Overflow
TABLE 10.7 Default Values for the Overflow Exception
EXAMPLE 10.7
10.3.6 Underflow
TABLE 10.8 Summary of the Flags and Results in Underflow Conditions
10.3.7 Inexact Result
10.4 ALGEBRAIC LAWS AND FLOATING-POINT
EXAMPLE 10.8
EXAMPLE 10.9
EXAMPLE 10.10
10.5 NORMALIZATION AND CANCELATION
EXAMPLE 10.11
EXAMPLE 10.12
TABLE 10.9 Internal Values for Example 10.12
EXAMPLE 10.13
EXAMPLE 10.14
TABLE 10.10 Internal Values for Example 10.13
10.6 EXERCISES
11 Floating-Point Data-Processing Instructions
11.1 INTRODUCTION
11.2 FLOATING-POINT DATA-PROCESSING INSTRUCTION SYNTAX
11.3 INSTRUCTION SUMMARY
TABLE 11.1 Cortex-M4 Floating-Point Instruction Summary
11.4 FLAGS AND THEIR USE
11.4.1 Comparison Instructions
11.4.2 The N Flag
TABLE 11.2 Floating-Point Status Flags
11.4.3 The Z Flag
11.4.4 The C Flag
11.4.5 The V Flag
EXAMPLE 11.1
TABLE 11.3 Example Compare Operations and Status Flag Settings
11.4.6 Predicated Instructions, or the Use of the Flags
EXAMPLE 11.2
EXAMPLE 11.3
EXAMPLE 11.4
FIGURE 11.1 FPSCR contents after the rounding mode change.
11.4.7 A Word about the IT Instruction
11.5 TWO SPECIAL MODES
11.5.1 Flush-to-Zero Mode
11.5.2 Default NaN
11.6 NON-ARITHMETIC INSTRUCTIONS
11.6.1 Absolute Value
11.6.2 Negate
EXAMPLE 11.5
TABLE 11.4 Examples of VABS and VNEG
11.7 ARITHMETIC INSTRUCTIONS
11.7.1 Addition/Subtraction
TABLE 11.5 Floating-Point Addition and Subtraction Instructions Operand and Exception Table
EXAMPLE 11.6
EXAMPLE 11.7
11.7.2 Multiplication and Multiply–Accumulate
11.7.2.1 Multiplication and Negate Multiplication
11.7.2.2 Chained Multiply–Accumulate
TABLE 11.6 Floating-Point Multiply Instructions Operand and Exception Table
EXAMPLE 11.8
TABLE 11.7 Chained Multiply-Accumulate Operations
11.7.2.3 Fused Multiply–Accumulate
EXAMPLE 11.9
TABLE 11.8 Fused Multiply–Accumulate Instructions Equivalent Operations
TABLE 11.9 Results of Example 11.9
11.7.3 Division and Square Root
TABLE 11.10 Floating-Point Divide Instruction Operand and Exception Table
TABLE 11.11 Floating-Point Square Root Instruction Operand and Exception Table
11.8 PUTTING IT ALL TOGETHER: A CODING EXAMPLE
FIGURE 11.2 Bisection method for two initial points and a computed third point.
11.9 EXERCISES
12 Tables
12.1 INTRODUCTION
12.2 INTEGER LOOKUP TABLES
FIGURE 12.1 A simple list in memory.
EXAMPLE 12.1
12.3 FLOATING-POINT LOOKUP TABLES
EXAMPLE 12.2
EXAMPLE 12.3
EXAMPLE 12.4 RECIPROCAL SQUARE ROOT ESTIMATION CODE
12.4 BINARY SEARCHES
FIGURE 12.2 Binary search table.
FIGURE 12.3 Two passes through a binary search.
FIGURE 12.4 Structure of an example table.
FIGURE 12.5 Assembly code for the binary search.
12.5 EXERCISES
13 Subroutines and Stacks
13.1 INTRODUCTION
13.2 THE STACK
FIGURE 13.1 A hardware stack in memory.
13.2.1 LDM/STM Instructions
EXAMPLE 13.1
FIGURE 13.2 LDM/STM operations.
13.2.2 PUSH and POP
EXAMPLE 13.2
FIGURE 13.3
FIGURE 13.4
13.2.3 Full/Empty Ascending/Descending Stacks
TABLE 13.1 Stack-Oriented Suffixes
EXAMPLE 13.3
13.3 SUBROUTINES
FIGURE 13.5 Stacking the Link Register during entry to a subroutine.
13.4 PASSING PARAMETERS TO SUBROUTINES
13.4.1 Passing Parameters in Registers
EXAMPLE 13.4
13.4.2 Passing Parameters by Reference
EXAMPLE 13.5
13.4.3 Passing Parameters on the Stack
EXAMPLE 13.6
FIGURE 13.6 Stack configuration.
EXAMPLE 13.7
13.5 THE ARM APCS
FIGURE 13.7 The ARM APCS specification for register usage.
EXAMPLE 13.8
13.6 EXERCISES
14 Exception Handling: ARM7TDMI
14.1 INTRODUCTION
14.2 INTERRUPTS
14.3 ERROR CONDITIONS
14.4 PROCESSOR EXCEPTION SEQUENCE
FIGURE 14.1 Register organization.
14.5 THE VECTOR TABLE
FIGURE 14.2 Exception vector table.
FIGURE 14.3 Example memory map with exception handlers.
14.6 EXCEPTION HANDLERS
14.7 EXCEPTION PRIORITIES
TABLE 14.1 ARM7TDMI Exception Priorities
14.8 PROCEDURES FOR HANDLING EXCEPTIONS
14.8.1 Reset Exceptions
14.8.2 Undefined Instructions
EXAMPLE 14.1
FIGURE 14.4 Exception flow diagram.
14.8.3 Interrupts
FIGURE 14.5 Three methods of handling interrupts.
14.8.3.1 Vectored Interrupt Controllers
FIGURE 14.6 STR910FAM32 microcontroller.
EXAMPLE 14.2
TABLE 14.2 Vector Table Showing IRQ Branch Instruction
TABLE 14.3 VIC0 Registers
FIGURE 14.7 Interrupt processing in the ARM7 pipeline.
14.8.3.2 More Advanced VICs
14.8.4 Aborts
14.8.4.1 Prefetch Aborts
14.8.4.2 Data Aborts
14.8.5 SVCs
FIGURE 14.8 Opcodes for SVC instructions.
14.9 EXERCISES
15 Exception Handling: v7-M
15.1 INTRODUCTION
15.2 OPERATION MODES AND PRIVILEGE LEVELS
FIGURE 15.1 Cortex-M4 operation modes.
FIGURE 15.2 CONTROL Register on the Cortex-M4.
EXAMPLE 15.1
FIGURE 15.3 Cortex-M4 operating in privileged Thread mode.
EXAMPLE 15.2
15.3 THE VECTOR TABLE
TABLE 15.1 Exception Types and Vector Table
15.4 STACK POINTERS
15.5 PROCESSOR EXCEPTION SEQUENCE
15.5.1 Entry
EXAMPLE 15.3
FIGURE 15.4 Exception stack frames.
FIGURE 15.5 Exception stack frame in memory.
TABLE 15.2 EXC_RETURN Value for the Cortex-M4 with Floating-Point Hardware
15.5.2 Exit
15.6 EXCEPTION TYPES
TABLE 15.3 Memory Management Fault Status Register (Offset 0xD28)
TABLE 15.4 Usage Fault Status Register (Offset 0xD2A)
15.7 INTERRUPTS
TABLE 15.5 Partial Vector Table for Interrupts on the Tiva TM4C1233H6PM Microcontroller
EXAMPLE 15.4
15.8 EXERCISES
16 Memory-Mapped Peripherals
16.1 INTRODUCTION
16.2 THE LPC2104
FIGURE 16.1 LPC2104/2105/2106 block diagram.
16.2.1 The UART
TABLE 16.1 UART Configuration Bits in the Control Register
16.2.2 The Memory Map
FIGURE 16.2 System memory map.
FIGURE 16.3 Memory map of UART0 on the LPC2104.
16.2.3 Configuring the UART
FIGURE 16.4 Pin descriptions for the LPC2104.
TABLE 16.2 PINSEL0 Register for Pin Configurations
16.2.4 Writing the Data to the UART
16.2.5 Putting the Code Together
16.2.6 Running the Code
16.3 THE LPC2132
FIGURE 16.5 The UART0 peripheral window.
FIGURE 16.6 Serial output window.
16.3.1 The D/A Converter
FIGURE 16.7 LPC2132 block diagram.
16.3.2 The Memory Map
FIGURE 16.8 LPC2132 memory map.
TABLE 16.3 DAC Register Bit Description
16.3.3 Configuring the D/A Converter
16.3.4 Generating a Sine Wave
16.3.5 Putting the Code Together
16.3.6 Running the Code
16.4 THE TIVA LAUNCHPAD
FIGURE 16.9 Simulation window with logic analyzer.
FIGURE 16.10 The Tiva Launchpad Evaluation Module.
FIGURE 16.11 Tiva™ TM4C123GH6PM microcontroller high-level block diagram.
16.4.1 General-Purpose I/O
16.4.2 The Memory Map
16.4.3 Configuring the GPIO Pins
TABLE 16.4 GPIO Port Locations
16.4.4 Turning on the LEDs
FIGURE 16.12 Masking of the GPIO bits.
16.4.5 Putting the Code Together
16.4.6 Running the Code
16.5 EXERCISES
17 ARM, Thumb and Thumb-2 Instructions
17.1 INTRODUCTION
17.2 ARM AND 16-BIT THUMB INSTRUCTIONS
TABLE 17.1 Architectures and Instruction Sets
FIGURE 17.1 ADD instruction format in ARM.
FIGURE 17.2 Thumb formats for ADD (immediate).
FIGURE 17.3 Dhrystone performance of ARM and 16-bit Thumb code.
17.2.1 Differences between ARM and 16-Bit Thumb
17.2.2 Thumb Implementation
FIGURE 17.4 The ARM7TDMI processor pipeline.
17.3 32-BIT THUMB INSTRUCTIONS
FIGURE 17.5 32-bit Thumb formats for ADD (immediate).
EXAMPLE 17.1
17.4 SWITCHING BETWEEN ARM AND THUMB STATES
FIGURE 17.6 Changing to Thumb state via BX instruction.
EXAMPLE 17.2
17.5 HOW TO COMPILE FOR THUMB
FIGURE 17.7 Linker generated veneers for ARM/Thumb interworking.
17.6 EXERCISES
18 Mixing C and Assembly
18.1 INTRODUCTION
18.2 INLINE ASSEMBLER
EXAMPLE 18.1
FIGURE 18.1 Multiply-accumulate with two Q15 numbers.
18.2.1 Inline Assembly Syntax
18.2.2 Restrictions on Inline Assembly Operations
18.3 EMBEDDED ASSEMBLER
EXAMPLE 18.2
18.3.1 Embedded Assembly Syntax
18.3.2 Restrictions on Embedded Assembly Operations
18.4 CALLING BETWEEN C AND ASSEMBLY
EXAMPLE 18.3
EXAMPLE 18.4
EXAMPLE 18.5
18.5 EXERCISES
Back Matter
Appendix A: Running Code Composer Studio
A.1 INTRODUCTION
A.2 RUNNING CODE ON THE CORTEX-M4
A.2.1 Creating a Cortex-M4 Project and Selecting a Device
FIGURE A.1 Creating a new project.
FIGURE A.2 Project options.
A.2.2 Creating Application Code
A.2.3 Building the Project and Running Code
FIGURE A.3 Properties dialog box.
FIGURE A.4 Sample code running in the debugger.
Appendix B: Running Keil Tools
B.1 INTRODUCTION
B.2 WORKING WITH AN ARM7TDMI
B.2.1 Creating an ARM7TDMI Project and Selecting a Device
FIGURE B.1 Creating a new project.
FIGURE B.2 Naming the project.
B.2.2 Creating Application Code
FIGURE B.3 Device database dialog box.
FIGURE B.4 Sample code.
FIGURE B.5 Adding a source file to the project.
B.2.3 Building the Project and Running Code
FIGURE B.6 Running code in the debugger.
B.3 WORKING WITH A CORTEX-M4
B.3.1 Creating a Cortex-M4 Project and Selecting a Device
FIGURE B.7 Creating a new project.
FIGURE B.8 Naming the project.
FIGURE B.9 Device database dialog box.
B.3.2 Creating Application Code
FIGURE B.10 Sample code.
FIGURE B.11 Running code in the debugger.
B.3.3 Building the Project and Running Code

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