Digital Systems Engineering 1st Edition by William Dally, John Poulton 052106175X 9780521061759
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ISBN 10: 052106175X
ISBN 13: 9780521061759
Author: William J. Dally, John W. Poulton
What makes some computers slow? Why do some digital systems operate reliably for years while others fail mysteriously every few hours? How can some systems dissipate kilowatts while others operate off batteries? These questions of speed, reliability, and power are all determined by the system-level electrical design of a digital system. Digital Systems Engineering presents a comprehensive treatment of these topics. It combines a rigorous development of the fundamental principles in each area with real-world examples of circuits and methods. The book not only serves as an undergraduate textbook, filling the gap between circuit design and logic design, but can also help practising digital designers keep pace with the speed and power of modern integrated circuits. The techniques described in this book, once used only in supercomputers, are essential to the correct and efficient operation of any type of digital system.
Table of contents:
1 Introduction to Digital Systems Engineering
1.1 Why Study Digital Systems Engineering?
1.2 An Engineering View of a Digital System
1.2.1 Feeds and Speeds
1.2.2 Signaling Conventions
Signaling Speed,
Signaling Power,
Signal Integrity,
Other Signaling Conventions,
1.2.3 Timing and Synchronization
Synchronous Timing,
Pipelined Timing,
Closed-Loop Timing,
Clock Distribution,
Synchronization,
1.2.4 Power Distribution
1.2.5 Noise
1.2.6 A Systems View of Circuits
1.3 Technology Trends and Digital Systems Engineering
1.3.1 Moore’s Law
1.3.2 Scaling of Chip Parameters
1.3.3 Scaling of Wires
Scaling of Power Distribution,
Scaling of On-Chip Communication,
Scaling of Off-Chip Communication,
1.3.4 High Levels of Integration Permit New Approaches
1.3.5 Digital Systems Problems and Solutions Continue to Change
1.4 Organization of this Book
1.5 Bibliographic Notes
1.6 Exercises
2 Packaging of Digital Systems
2.1 A Typical Digital System
2.2 Digital Integrated Circuits – On-Chip Wiring
2.3 Integrated Circuit Packages
2.3.1 Wire Bonds and Solder Balls
2.3.2 Package Types
2.3.3 Package Manufacturing Processes
2.3.4 Multichip Modules
2.3.5 A Typical Package Model
Physical Construction,
Package Electrical Model,
2.4 Printed Circuit Boards
2.4.1 PC Board Construction
2.4.2 Electrical Properties
2.4.3 Manufacturing Process
2.4.4 Vias
2.4.5 Dimensional Constraints
2.4.6 Mounting Components: Surface-Mount and Through-Hole
2.4.7 Sockets
2.5 Chassis and Cabinets
2.6 Backplanes and Mother Boards
2.6.1 Daughter Cards
2.6.2 Backplanes
2.7 Wire and Cable
2.7.1 Wires
2.7.2 Signaling Cables
Coaxial Cable,
Ribbon Cable,
Twisted Pair,
Flex-Circuit Cable,
2.7.3 Bus Bars
2.8 Connectors
2.8.1 PC Board Connectors
2.8.2 Interposers
2.8.3 Elastomeric Connectors
2.8.4 Power Connectors
2.8.5 Wire and Cable Connectors
Wire Harness Connectors,
Coaxial Connectors,
Ribbon-Cable Connectors,
Methods of Attachment,
2.9 Optical Communication
2.9.1 Optical Transmitters
LEDs,
Laser Diodes,
2.9.2 Optical Fiber
Multimode Fiber,
Single-Mode Fiber,
Optical Connectors,
2.9.3 Optical Receivers
2.9.4 Multiplexing
Wavelength-Division Multiplexing,
Time-Division Multiplexing,
2.9.5 Optical Amplifiers
2.9.6 Free-Space Optical Interconnect
2.10 Radio Communication
2.10.1 A Typical Digital Radio
2.10.2 The Power Equation
2.10.3 Modulation
Amplitude Modulation,
Phase Modulation (PM),
Frequency Modulation,
Code-Division Multiple Access (CDMA),
2.10.4 Multipath
2.11 Bibliographic Notes
2.12 Exercises
3 Modeling and Analysis of Wires
3.1 Geometry and Electrical Properties
3.1.1 Resistance
3.1.2 Capacitance
3.1.3 Inductance
3.2 Electrical Models of Wires
3.2.1 The Ideal Wire
3.2.2 The Transmission Line
Partial Differential Equation,
Impedance of an Infinite Line,
Frequency-Domain Solution,
Signal Returns,
Lumped Models of Transmission Lines,
3.3 Simple Transmission Lines
3.3.1 Lumped Wires
Lumped Capacitive Loads,
Lumped Resistive Lines,
Lumped Inductive Lines,
Lumped Models of Impedance Discontinuities,
3.3.2 RC Transmission Lines
Step Response of an RC Line,
Low-Frequency RC Lines,
3.3.3 Lossless LC Transmission Lines
Traveling Waves,
Impedance,
Driving LC Transmission Lines,
Reflections and the Telegrapher’s Equation,
Some Common Terminations,
Source Termination and Multiple Reflections,
Arbitrary Termination,
Standing Waves,
Summary,
3.3.4 Lossy LRC Transmission Lines
Wave Attenuation,
DC Attenuation,
Combined Traveling Wave and Diffusive Response,
The Skin Effect,
3.3.5 Dielectric Absorption
3.4 Special Transmission Lines
3.4.1 Multidrop Buses
3.4.2 Balanced Transmission Lines
3.4.3 Common- and Differential-Mode Impedance
3.4.4 Isolated Lines
AC Coupling,
Optical Isolation,
3.5 Wire Cost Models
3.5.1 Wire Area Costs
3.5.2 Terminal Costs
3.6 Measurement Techniques
3.6.1 Time-Domain Measurements
The Time-Domain Reflectometer,
Rise Time and Resolution,
Lumped Discontinuities,
Transmission Measurements,
Cross Talk Measurements,
3.6.2 Network Analysis
3.6.3 CAD Tools for Characterizing Wires
Spreadsheets,
Two-Dimensional Electromagnetic Field Solvers,
Signal Integrity Software Packages,
3D Electromagnetic Field Solvers,
3.7 Some Experimental Measurements
3.7.1 Frequency-Dependent Attenuation in a PC Board Trace
DC Resistance and Attenuation Calculations,
High-Frequency Attenuation Factors,
3.7.2 Cross Talk in Coupled Lines
Coupled Embedded Striplines,
Coupled Inhomogeneous Lines,
Coupling Between Lines at Right Angles,
3.7.3 Inductive and Capacitive Discontinuities
3.7.4 Measurement of IC Package Parasitics
3.7.5 Measurement Practice
3.8 Bibliographic Notes
3.9 Exercises
4 Circuits
4.1 MOS Transistors
4.1.1 MOS Device Structure
4.1.2 Current-Voltage Characteristics
Threshold Voltage,
Resistive Region,
Saturation Region,
p-Channel FETs,
Channel-Length Modulation,
Body Effect,
Velocity Saturation,
Subthreshold Conduction,
Typical I–V Curves,
Enhancement and Depletion Devices,
4.1.3 Parameters for a Typical 0.35-μm CMOS Process
4.2 Parasitic Circuit Elements
4.2.1 Parasitic Capacitors
Gate Capacitance,
Source and Drain Diodes,
4.2.2 Parasitic Resistance
4.2.3 A Typical Device
4.2.4 SPICE Models
4.3 Basic Circuit Forms
4.3.1 Switch Networks
Pass Gates,
Logic with Switches,
Circuits Using Switches,
Transient Analysis of Switch Networks,
4.3.2 The Static CMOS Gate
Inverter DC Transfer Characteristics,
Inverter Gain,
Transient Response,
Propagation Delay and Nonzero Rise Time,
The Effect of Input Rise Time on Delay,
Asymmetrical Sizing,
Miller-Effect Capacitance,
Gain-Bandwidth Product,
The Exponential Horn,
SPICE Simulations of Gates,
4.3.3 Dynamic Circuits
The Dynamic Latch,
Precharged Gates,
Domino Logic,
Dual-Rail Domino,
Bootstrap Circuits,
4.3.4 Source Followers and Cascodes
Source Follower,
Cascode,
4.3.5 Current Mirrors
The Basic Current Mirror,
The Cascode Current Mirror,
4.3.6 The Source-Coupled Pair
V-I Characteristics of the Source-Coupled Pair,
Differential Circuit Analysis,
Differential Loads,
Mode Coupling,
FET Resistors,
A Simple Differential Amplifier,
4.3.7 Regenerative Circuits and Clocked Amplifiers
4.4 Circuit Analysis
4.4.1 Qualitative Circuit Analysis
Qualitative Analysis of a Differential Amplifier,
Qualitative Analysis of a Voltage-Controlled Oscillator,
4.4.2 Power Dissipation
Power Dissipation of a Static CMOS Gate,
Energy-Delay Product of a CMOS Gate,
AC Versus DC Power,
Power Dissipation of Source-Coupled FET Logic,
4.5 Bibliographic Notes
4.6 Exercises
5 Power Distribution
5.1 The Power Supply Network
5.1.1 Local Loads and Signal Loads
Local Loads,
Signal Loads,
5.1.2 Inductive Power Supply Noise
5.2 Local Regulation
5.2.1 Clamps and Shunt Regulators
5.2.2 Series Regulators
Linear Regulator,
Switching Regulator,
5.3 Logic Loads and On-Chip Power Supply Distribution
5.3.1 Logic Current Profile
5.3.2 IR Drops
5.3.3 Area Bonding
5.3.4 Metal Migration
5.3.5 On-Chip Bypass Capacitors
5.3.6 Symbiotic Bypass Capacitance
5.4 Power Supply Isolation
5.4.1 Supply-Supply Isolation
5.4.2 Signal-Supply Isolation
5.5 Bypass Capacitors
5.6 Example Power Distribution System
5.7 Bibliographic Notes
5.8 Exercises
6 Noise in Digital Systems
6.1 Noise Sources in a Digital System
6.2 Power Supply Noise
6.2.1 Single Supply Noise
6.2.2 Differential Supply Noise
6.2.3 Internal and External Supply Noise
6.3 Cross Talk
6.3.1 Cross Talk to Capacitive Lines
Coupling to a Floating Line,
Coupling to a Driven Line,
Typical Capacitance Values,
Capacitive Cross Talk Countermeasures,
6.3.2 Cross Talk to Transmission Lines
Capacitive and Inductive Coupling of Transmission Lines,
Lumped Inductive Coupling,
Near- and Far-End Cross Talk,
Typical Coupling Coefficients,
Transmission Line Cross Talk Countermeasures,
6.3.3 Signal Return Cross Talk
6.3.4 Power Supply Cross Talk
6.4 Intersymbol Interference
6.4.1 Impedance Mismatch and Reflections
6.4.2 Resonant Transmitter Circuits
6.4.3 Inertial Delay and Hidden State
6.5 Other Noise Sources
6.5.1 Alpha Particles
6.5.2 Electromagnetic Interference
6.5.3 Process Variation
Typical Process Variations,
Inverter Offset,
Inverter Compensation,
Differential Pair Offset,
6.5.4 Thermal (Johnson) Noise
6.5.5 Shot Noise
6.5.6 Flicker or 1/f Noise
6.6 Managing Noise
6.6.1 Bounded Noise and Noise Budgets
Proportional Noise Sources,
Fixed Noise Sources,
Overall Noise Budgets,
6.6.2 Gaussian Noise and Bit Error Rates
6.7 Bibliographic Notes
6.8 Exercises
7 Signaling Conventions
7.1 A Comparison of Two Transmission Systems
7.1.1 Signal Energy and System Power
7.1.2 Noise Immunity Versus Noise Margin
7.1.3 Delay
7.1.4 Discussion
7.2 Considerations in Transmission System Design
7.3 Signaling Modes for Transmission Lines
7.3.1 Transmitter Signaling Methods
Current-Mode Transmission,
Voltage-Mode Transmission,
Transmitter Signal-Return Cross Talk,
Bipolar Versus Unipolar Signaling,
Transmitter-Generated References,
7.3.2 Receiver Signal Detection
Generating the Receiver Reference,
Receiver Return Cross Talk,
Power Supply Noise,
7.3.3 Source Termination
Noise Considerations,
Power Dissipation,
Current-Mode Source Termination,
7.3.4 Underterminated Drivers
7.3.5 Differential Signaling
Symmetric Transmission Lines,
7.4 Signaling Over Lumped Transmission Media
7.4.1 Signaling Over a Capacitive Transmission Medium
Voltage-Mode Signaling,
Current-Mode Signaling,
Resistive Voltage Divider,
Pulsed Signaling,
Return-to-Zero (Precharged) Pulsed Signaling,
Band-Limited Pulsed Signaling,
References,
7.4.2 Signaling over Lumped LRC Interconnect
Rise-Time Control,
Adding Parallel Termination,
Reducing Power Supply Noise,
7.5 Signal Encoding
7.5.1 Number of Signal Levels
7.5.2 Signal Magnitude
Hysteresis,
7.5.3 Signal Transfer Function
7.5.4 Error Correcting Codes
7.5.5 Pulsed Signaling
7.5.6 Signal Level and Delay
7.6 Bibliographic Notes
7.7 Exercises
8 Advanced Signaling Techniques
8.1 Signaling over RC Interconnect
8.1.1 Circuit Model
8.1.2 Repeaters
8.1.3 Increasing Wire Width and Spacing
8.1.4 Overdrive of Low-Swing RC Lines
8.2 Driving Lossy LC Lines
8.2.1 The Lone Pulse
8.2.2 Equalization of LRC Lines
8.3 Simultaneous Bidirectional Signaling
8.3.1 Current-Mode Bidirectional Signaling
8.3.2 Bidirectional Signaling Waveforms
8.3.3 Differential Simultaneous Bidirectional Signaling
8.3.4 Voltage-Mode Simultaneous Bidirectional Signaling
8.3.5 Reverse-Channel Cross Talk
8.4 AC and N of M Balanced Signaling
8.4.1 Terminology
DC Offset,
Run Length,
Disparity or Digital-Sum Variation (DSV),
8.4.2 Codes for DC-Balancing Signals
Nonoverlapping Block Codes,
Running-Disparity Encoding,
Framing,
Burst-Error Length,
The 8b/10b Code,
DC Restoration,
8.4.3 Spatial N of M Balanced Signaling
Coding Efficiency,
Systematic Encoding,
8.5 Examples
8.5.1 Logic Signaling
8.5.2 SRAM Bit Lines
8.5.3 Signaling Over Long On-Chip Wires
8.5.4 Signaling Chip-to-Chip on a Board
8.5.5 Signaling across a Cable
8.6 Bibliographic Notes
8.7 Exercises
9 Timing Conventions
9.1 A Comparison of Two Timing Conventions
9.1.1 Skew and Jitter Analysis
9.1.2 Allowable Clock Rates
9.1.3 Discussion
9.2 Considerations in Timing Design
9.3 Timing Fundamentals
9.3.1 Timing Nomenclature
Delay and Transition Times,
Periodic Signals,
Maximum Absolute Value, Peak-to-Peak, and RMS,
9.3.2 Timing Properties of Delay Elements
9.3.3 Timing Properties of Combinational Logic
9.3.4 Timing Properties of Clocked Storage Elements
Edge-Triggered Flip-Flop,
Level-Sensitive Latch,
Double-Edge-Triggered Flip-Flop,
9.3.5 The Eye Diagram
9.4 Encoding Timing: Signals and Events
9.4.1 Encoding Aperiodic Events
Dual-Rail Signaling,
Return-to-Zero (RZ)/Nonreturn-to-Zero (NRZ) Signaling,
Clocked Signaling and Bundling,
Ternary Signaling,
9.4.2 Encoding Periodic Signals
Required Transition Frequency,
Bit Stuffing,
Phase-Encoding,
9.5 Open-Loop Synchronous Timing
9.5.1 Global Clock, Edge-Triggered Timing
Minimum Delay Constraint,
Maximum Delay Constraint,
9.5.2 Level-Sensitive Clocking
Basic Two-Phase Clocking,
Borrowing Time,
Effect of Skew,
Qualified Clocks,
Signal Labeling for Two-Phase Clocking,
Single-Phase or Zero Nonoverlap Clocking,
9.5.3 Pipeline Timing
Optimum Clock Delay,
Level-Sensitive Pipeline Timing,
Pipelines With Feedback,
9.6 Closed-Loop Timing
9.6.1 A Simple Timing Loop
Residual Error,
Loop Dynamics,
9.6.2 Phase Comparators
Flip-Flop Phase Comparator,
Exclusive-OR (XOR) Phase Comparator,
Sequential Phase and Frequency Comparator,
9.6.3 Variable Delay Line
9.6.4 Bundled Closed-Loop Timing
Canceled and Uncanceled Sources of Timing Uncertainty,
Integrating Receivers,
9.6.5 Per-Line Closed-Loop Timing
9.6.6 Phase-Locked Loops
Voltage-Controlled Oscillators,
Frequency Comparator,
Loop Dynamics and Loop Filter,
Reducing Jitter with a Phase-Locked Loop,
9.6.7 Oversampling Clock Recovery
9.7 Clock Distribution
9.7.1 Off-Chip Clock Distribution
Clock Distribution Trees,
Phase-Locked Clock Distribution Networks,
Salphasic Clock Distribution,
Round-Trip Distribution,
9.7.2 On-Chip Clock Distribution
On-Chip Clock Trees,
Mesh Distribution,
Jitter in On-Chip Clock Distribution,
9.8 Bibliographic Notes
9.9 Exercises
10 Synchronization
10.1 A Comparison of Three Synchronization Strategies
10.2 Synchronization Fundamentals
10.2.1 Uses of Synchronization
Arbitration of Asynchronous Signals,
Sampling Asynchronous Signals,
Crossing Clock Domains,
10.2.2 Synchronization Failure and Metastability
Synchronizer Dynamics and Synchronization Time,
Metastability,
Probability of Synchronization Failure,
Example Synchronizer Calculation,
Completion Detection,
Common Synchronizer Mistakes,
10.2.3 Clock Domains
Independent Clock Rates,
Simplified Clock Distribution,
Pipelined Signal Timing Eliminates Cable Delay Constraints,
Aperiodic Clocks,
10.2.4 Classification of Signal-Clock Synchronization
10.3 Synchronizer Design
10.3.1 Mesochronous Synchronizers
Delay-Line Synchronizer,
Two-Register Synchronizer,
FIFO Synchronizer,
Brute-Force Synchronization,
10.3.2 Plesiochronous Synchronizers
A Plesiochronous FIFO Synchronizer,
Data Rate Mismatch,
Detecting Phase Slip,
Null Symbols and Flow Control,
10.3.3 Periodic Asynchronous Synchronizers
Clock Predictor Circuit,
Periodic Synchronizer,
10.3.4 General Purpose Asynchronous Synchronizers
Waiting Synchronizer,
Asynchronous FIFO Synchronizer,
10.4 Asynchronous Design
10.4.1 Stoppable Clocks
10.4.2 Asynchronous Signaling Protocols
Four-Phase Asynchronous Signaling,
Two-Phase Asynchronous Signaling,
The Weak Conditions,
10.4.3 Asynchronous Module Design Methods
State Diagrams,
Concurrency and Choice,
Trajectory Maps for Designing Asynchronous Sequential Logic,
Set-Reset Excitation Equations,
Arbitration and Circuits with Choice,
Delay-Insensitive versus Matched-Delay Modules,
10.4.4 Composition of Asynchronous Circuits
Asynchronous Combinational Blocks,
Align Blocks and Self-Timed Pipelines,
Cyclic Asynchronous Circuits,
10.5 Bibliographic Notes
10.6 Exercises
11 Signaling Circuits
11.1 Terminations
11.1.1 On-Chip Versus Off-Chip Termination
11.1.2 FET Terminations
11.1.3 Adjustable Terminators
Digital Versus Analog Adjustment,
Binary Versus Thermometer Digital Adjustment Codes,
11.1.4 Automatic Terminator Adjustment
Automated Adjustment Controllers,
Thermometer-Coded Controllers,
Self-Series Termination Control,
11.2 Transmitter Circuits
11.2.1 Voltage-Mode Driver
Break-Before-Make Action,
Pulse-Generating Driver,
Tristate Driver,
Open-Drain Outputs,
11.2.2 Self-Series-Terminating Drivers
11.2.3 Current-Mode Drivers
Saturated FET Driver,
Current-Mirror Drivers,
Differential Current-Steering Driver,
Bipolar Current-Mode Drivers,
11.2.4 Rise-Time Control
Segmented Current Driver,
The Problem with RC Rise-Time Control,
Segmented Voltage Driver,
Segmented Self-Series Terminated Driver,
11.2.5 Drivers for Lumped Loads
On-Chip Drivers for Capacitive Loads,
Off-Chip Drivers for LRC Loads,
11.2.6 Multiplexing Transmitters
11.3 Receiver Circuits
11.3.1 Receivers Using Static Amplifiers
The Inverter As a Receiver,
Source-Coupled FET Receivers,
11.3.2 Receivers Using Clocked Differential Amplifiers
11.3.3 Integrating Amplifiers
An Integrating Amplifier,
Receiver Impulse Response,
A Matched-Filter Receive Amplifier,
11.3.4 Demultiplexing Receivers
11.4 Electrostatic Discharge (ESD) Protection
11.4.1 ESD Failure Mechanisms
Field-Induced Failures,
Thermally Induced Failures,
11.4.2 ESD Protection Devices
Primary Shunt,
Series Resistor,
Secondary Shunt,
Protecting Output Drivers,
Guard Rings,
Wiring and Contacting,
11.5 An Example Signaling System
11.5.1 Transmitter
Multiphase Clock Generator,
Output Driver,
Bias Generator,
Predriver,
Latches and Pass-Gate Clocking Network,
Package Model,
Transmission Line Model,
Simulation Results for Package and Transmission-Line Models,
Termination Schemes,
Effectiveness of Slew-Rate Control,
Noise Modeling,
11.5.2 Receiver
Phase Shifter and Multiphase Clock Generator,
Samplers,
Retiming Latches,
Clock Adjuster,
11.6 Bibliographic Notes
11.7 Exercises
12 Timing Circuits
12.1 Latches and Flip-Flops
12.1.1 Level-Sensitive Latches
Dynamic Latches,
CMOS Static Storage Element,
CMOS Static Latches,
12.1.2 Edge-Triggered Flip-Flops
Auxiliary Control Inputs,
True Single-Phase-Clocked (TSPC) Flip-Flops,
Differential Edge-Triggered Flip-Flop,
Double-Edge-Triggered Flip-Flops,
12.1.3 Failure Mechanisms in Flip-Flops and Latches
Race-Through,
Dynamic Node Discharge,
Power Supply Noise,
Clock Slope,
Charge Sharing,
12.2 Delay Line Circuits
12.2.1 Inverter Delay Lines
Delay Adjustment Range,
Power-Supply Rejection in Inverter Delay Elements,
Inverters with Regulated Supply Voltage,
12.2.2 Differential Delay Elements
Adjustable PFET Resistor,
Replica-Biased Delay Line,
Adjustment Range for Replica-Bias Delay Lines,
Static Supply Sensitivity for the Replica-Biased Delay Stage,
Dynamic Supply Sensitivity,
12.2.3 Circuit and Layout Details
Replica Control Loop Stability,
Power Routing and Bypassing,
Matching and Balancing,
Substrate Noise,
12.2.4 Other Differential Timing Components
Small-Swing to Full-Swing Buffers,
Interpolators,
Duty-Cycle Correctors,
Clock Input Conditioning,
12.3 Voltage-Controlled Oscillators
12.3.1 First-Order Oscillators
Array Oscillators,
12.3.2 Second-Order Oscillators
Crystal Oscillators,
Frequency Multiplication,
Lumped-Element Oscillators,
12.4 Phase Comparators
12.4.1 XOR Comparator
12.4.2 Edge-Triggered Flip-Flop Phase Detector
12.4.3 Sequential Phase Detectors
12.5 Loop Filters
12.5.1 RC Loop Filters
12.5.2 Charge Pump Filters
Charge Pump Control Voltage Ripple,
Self-Biased Loop Filters,
12.5.3 Delay-Locked Loop Filters
Self-Biased DLL Loop Filter,
Switched-Capacitor Loop Filters,
Loop Initialization,
“Turbo” Mode,
“Bang-Bang” Controllers,
Digital Loop Controllers,
12.6 Clock Aligners
12.6.1 PLL Versus DLL Implementations
12.6.2 Simple DLL-Based Aligners
12.6.3 Phase-Based Aligners
12.6.4 A Hybrid Phase/Delay-Based Clock Aligner
12.7 Bibliographic Notes
12.8 Problems
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